Example: Design a synchronous reset 3 digital countor

Analysis: First, we can see what signals. RST, 3 digits, clock signals. (Use the 2 -router. Rebate and not reset)

Second, how to achieve it, one clock comes over, remember the number of times at one time, save (use D trigger), and 0 after full;

Finally, follow the above analysis and perform the program.

module cunt3 (clk, rst, count); 
  input clk, rst; 
  output [2: 0] Count; 
   Reg [2: 0] count; 
 
 always @(clk) // synchronous reset 
   begin 
      if (rst == 1) 
       count = 0; 
      elseif (count == 3'b111) // This is a D trigger, q = count, d = count+1; 
            count = 0; 
      else 
       connent = count+1; 
    end 
 endmodule

Module cunt3 (clk, rst, count); 
  input clk, rst; 
  output [2: 0] Count; 
   Reg [2: 0] count; 
 
 always @(posedge clk) // synchronous reset 
   begin 
      if (rst == 1) 
       count <= 0; 
      elseif (count == 3'b111) // This is a D trigger, q = count, d = count+1; 
            count <= 3'b0; 
      else 
       Count <= Count+3'b1; 
    end 
 endmodule

has been modified above, so due to timing logic circuit, therefore. Use non -blocking assignment. Q is 3 digits, so add 3’b1,

1. Input code, select Processing> START> Analysis & Elaboration
2. Tools > Netlist viewer > RTL viewer
3. After the above steps, the following circuit is obtained.

From the figure, we can see that there are two 2 selected 1 selectioner and a D trigger (because 3 digits of data are stored, 3 D triggers are required), and there is also a addter and a comparator.

Therefore, it can be shown that those components can be used from the program to better understand the purpose of the program.