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“XDC Convention Skills” series discusses the setting method, constraints and some places that are easily confused. We mentioned that the constraints are designed for the design service. The XDC writing into Vivado is actually the target set by the user. The implementation process of Vivado’s FPGA design must be carried out with the constraints in XDC. So:

• How to verify whether the design after implementation meets the timing requirements?

  How to determine whether some constraints are successfully set up before starting layout wiring?

• How to verify the priority of constraints?
• These all need to use static timing analysis tools in vivado. So let’s start with how to read and use Timing Report.Static timing analysisStatic Timing Analysis, referred to as STA, uses exhaustive analysis methods to extract all the time order paths existing in the entire circuit. Calculate the delay of the transmission of signals on these paths, check whether the establishment and maintenance time of the signal meets the timing sequential time order It is required to find out errors that violate the sequential constraints and report through the analysis of the maximum path delay and minimum path delay. The STA can exhaust all the paths without input vectors, and the operating speed is fast, the memory is small, and the coverage rate is extremely high. It can not only conduct a comprehensive timing function inspection of the chip design design. Therefore, STA is not only a must for digital integrated circuit design Timing Sign-OFF, but also more and more used in the verification and commissioning of design. STA is also important in FPGA design, but unlike the design of general digital integrated circuits, the static timing analysis tools in FPGA design are generally integrated in the implementation tools provided by chip manufacturers. There is even no independent interface in Vivado, but is implemented through several specific timing report commands.OCV and PVTEven if the same FF is the same, the delay is different under different operating conditions on the same chip. We call this phenomenon OCV (on-chip variation). OCV represents the sequential deviation inside the chip. Although it is small, it must also be strictly considered in the sequential analysis. The main reasons for OCV are the three aspects: PVT (Process / Voltage / TEMPARATURATURATURAR), and what STA needs to do is to analyze the sequence path for different technical corners under different process corners, thereby ensuring that the design is under any conditions under any conditions. Can meet the requirements of timing and work normally. The impact of PVT on chip performance is usually shown in the figure below, Different PVT conditions form different CORNER. In addition, the impact of RC Corner must be considered in digital circuit design. After the arrangement is arranged and combined, there may be more than ten types of Corner to analyze. However, the static timing analysis in FPGA design generally only considers Best Case and Worst Case, also known as Fast Process Corner and Slow Process Corner, which correspond to extreme PVT conditions, respectively. Multi-Cornervivado STA supports multi-corner timing analysis, which will analyze the timing under the above two CORNER at the same time, and then report the worst situation. Because there will be a certain range of changes in each Corner, timing analysis will also take into account the maximum delay and minimum delay under each class. If a design can meet the timing requirements under Best Case and Worst Case, it can be calculated that this design can maintain normal work under any operating conditions it allowed. Here we remind everyone not to be mislead by Corner’s name. In fact, the same path may be satisfied in Slow Corner but sometimes illegal in the Fast Corner. But the timing report you see in Vivado will only show the worst case selected after the two CORNER analysis. In the case of special needs, you can via config_timing_corners -corner in vivado-Dlay_type to select an analysis that applies some Corner to Setup and/or Hold. The graphical interface of the REPORT TIMING SUMMARY and Report Timing can also be adjusted to the Corner through Timer Setting. For details, please refer to the description later. In this way, the time -order analysis method of OCV will also apply different delay data when processing the common clock path of the same path, so as to obtain more pessimistic data. In order to truly reflect the road delay, this delay must be corrected. This is the CRPR (CLOCK Reconvergeence PESSIMISM Removal). After careful observation of the timing report, you can find that before the Slack of the report path, a line shows that the CLock PESSIMISM has been considered. When the Setup Check is performed, a certain CLOCK PEssimism will be added, and the CLock PEssimism will be reduced when Hold Check. The following figure shows the source of CRPR and the specific embodiment of the Vivado timing report.Time order command and reportvivado The commands used for timing analysis are mainly the following two, and they all have the corresponding graphical settings interface.
• Report_timing_summary is mainly used for the implementation of Timing Sigh-Off
• Report_timing is mainly used for interactive constraint verification and more detailed and specific timing reports and analysis
• report_timing_summary Let’s take a look at the report_timing_summary. In fact, not only can it run after the layout wiring, after the combination, but even every small step in the process of implementation, so as to get a global timing report. You can change the contents of the report after clicking the report timing summary in Vivado IDE, such as the number of paths reported in each clock domain, whether Setup and HOLD are all reported, and so on. Every time you change the option, you can see the COMMAND column under the window display the corresponding TCL command. After modifying the settings, you can directly press the OK key to confirm the execution, or you can copy the command displayed by the Command column to execute later in the TCL script.Summary

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