# jsitent topic (17) Linear feedback shift register (LFSR) Andy

2022-12-20   ES

hdlbits URL: https://hdlbits.01xz.net/wiki/main_page

# Preface The

displacement register is a common device that generates signals and sequences. It is divided into two categories: linear and non -linear. Among them, linear feedback shifting registers (LFSR) refers to the output of the previous state, and the linear function of the output is used as the input shift register.Different or computing is the most common single -comparison function: After some bits of the register are input or operate as input, and then the comparison in the register is shifted as a whole.

linear feedback shift register applicationIncludes pseudo -random numbers, pseudo -random noise sequences, fast digital counter, and disturbers. The application of linear feedback displacement registers in hardware and software is very common. The mathematical principles used in the circulating redundancy verification to quickly verify the error of transmitting errors are closely related to the linear feedback transfer register.

# 1、5-bit LFSR

## Question

The following diagram shows a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. (Tap positions are usually numbered starting from 1). Note that I drew the XOR gate at position 5 for consistency, but one of the XOR gate inputs is 0.

## My design

Look at the picture design, directly paste the code

``module top_module(``    input clk,``    input reset,    // Active-high synchronous reset to 5'h1``    output [4:0] q``);``​``    [email protected](posedge clk) begin``        if(reset) ``            q <= 5'h1;``        else begin``            q <= {q[0],q[4],q[3]^q[0],q[2:1]};``        end ``    end``​``​``endmodule``

# 2、32-bit LFSR

## Questions

Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1.

## My design

is the same as the above principle, the code is as follows:

``module top_module(``    input clk,``    input reset,    // Active-high synchronous reset to 32'h1``    output [31:0] q``); ``    [email protected](posedge clk) begin``        if(reset) q <= 32'h1;``        else begin``            q <= {q[0],q[31:23],q[22]^q[0],q[21:3],q[2]^q[0],q[1]^q[0]};``        end``        ``    end``endmodule``

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