IOS development Homekit (2) lu

2023-01-19   ES  

– ARM interrupt system summary
At first look at the ARM interrupt system, it feels a bit messy, writing something, I hope it is a bit helpful to everyone
Interrupt Detailed Establishment Process (1)
First of all, let’s look at two things first.


HandleReset # 4

HandleUndef # 4

HandleSwi # 4

HandlePrefetch # 4

HandleAbort # 4

HandleReserv # 4

HandleIrq # 4

HandleFiq # 4

小 这里: The^here is map,# is FIELD
is also a interrupt vector table that starts in Darm’s BANK0 to store the inlet address of the interrupt program.


DCD UserCodeArea

DCD SystemUndefinedHandler

DCD SystemSwiHandler

DCD SystemPrefetchHandler

DCD SystemAbortHandler

DCD SystemReserv

DCD SystemIrqHandler

DCD SystemFiqHandler

This table is stored in the inlet address of the interrupt processing function in the assembly program, each of which corresponds to a interrupt function.

Below we analyze from the beginning of the program:


B Reset_Handler

B Undefined_Handler

B SWI_Handler

B Prefetch_Handler

B Abort_Handler

NOP Reserved vector

B IRQ_Handler

B FIQ_Handler


SUB sp, sp, #4

STMFD SP!, {R0} FD full stack execution stack operation.
ldr R0, = handlefiq compilation of the processing function address, and then jump to C, in DRAM.
LDR R0, [R0] Interrupt vector address to R0.
str r0, [SP, # 4] Interrupt vector address Give
LDMFD sp!, {r0, pc}

At the beginning of the program, the default interrupt call function is established first. This process must be very familiar.
First execute the pressure stack, and then gives the interrupt entry address. This handlefiq is one of the interrupt vectors we mentioned earlier in DRAM.
Among the four bytes of Handlefiq, the entrance address of the assembly interrupt processing function is placed.

What is the address of the assembly interrupt processing function in the DRAM interrupt vector table?

The other table we mentioned above played a role. Look at the procedure below:

LDR r0, =HandleReset

LDR r1, =ExceptionHandlerTable

MOV r2, #8


LDR r3, [r1], #4

STR r3, [r0], #4

SUBS r2, r2, #1 Down Count

BNE Exceptloop; take it from the table to the space behind HandlerEset
This section copy the address of the interrupt processing function in ExceptionHandlertable to the interrupt vector table in DRAM. So the two are linked
After the jump of the execution program starts, it jumps naturally to ******** Handler. One of the real processing functions is shown below:

It actually only called the interrupt processing function of the C language, and nothing else was done.


STMFD sp!, {r0-r7, lr}

BL ISR_FiqHandler

LDMFD sp!, {r0-r7, lr}

SUBS pc, lr, #4

It actually only called the interrupt processing function of the C language, and nothing else was done.
void ISR_FiqHandler(void)


IntOffSet = (U32)INTOFFSET;


(*InterruptHandlers[IntOffSet>>2])(); // Call interrupt service routine



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